1. Field of the Invention
This invention relates to the fabrication of semiconductor devices. Still more particularly, this invention relates to the integrated fabrication on a single wafer of both MNOS and CMOS devices by a combination of diffusion and ion implantation techniques.
2. Description of the Prior Art
Known present processes for the fabrication of metal nitride oxide silicon (MNOS) memory transistors require the use of epitaxial silicon wafers for the substrate material. However, normal MOS devices are usually fabricated in bulk silicon wafers. The cost differential between these two types of substrate starting materials is, at present, $5.00 per wafer for bulk silicon versus $15.00 to $20.00 per wafer for epitaxial silicon wafers. Additionally, in order to achieve peripheral circuit operation during the time when the MNOS transistors are accessed for memory erase, the peripheral circuits must be isolated from the MNOS substrate due to the high voltages involved in the memory erase operation for the MNOS transistors. This isolation is normally accomplished by isolation moat diffusions which require high temperatures and long diffusion time periods for their implementation. For these and other reasons, it has not been cost competitive to combine MNOS transistor technology with other typical MOS technologies on the same wafer.
Complimentary metal oxide semiconductor (CMOS) devices offer the important advantages of relatively high access speed, low power dissipation and radiation tolerance. Until relatively recently, most all MNOS large scale integration (LSI) devices and circuits have been based on p channel MOS technology. However, within the last few years, MNOS transistor devices have been successfully implemented in n channel MOS technology as well. This has created the potential for the fabrication of MNOS memory transistors based upon the CMOS technology.